1. Field of the Invention
The present invention relates to a plasma display panel and method for manufacturing the same, and more particularly, to a plasma display panel and method for manufacturing the same wherein the quality of an image can be improved by preventing an erroneous discharge.
2. Description of the Background Art
Various flat panel display devices have recently been developed which can reduce their heavy weight and large volume as shortcomings of the cathode ray tube. These flat panel display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (hereinafter, referred to as “PDP”), an electro-luminescence (EL) display device and so on.
Among them, the PDP is a display device using a gas discharge and has a competitive advantage in that it can be easily fabricated as a large-sized panel. An example of a representative PDP includes a three-electrode AC surface discharge type PDP having three electrodes and driven by an AC voltage, as shown in FIG. 3.
A discharge cell of the PDP shown in FIG. 1 includes an address electrode 12X formed on a lower substrate 18, and a pair of sustain electrodes formed on the underside of an upper substrate 10, i.e., a scan/sustain electrode 12Y and a common sustain electrode 12Z. In FIG. 1, the lower substrate 18 is shown with it rotated by 180°.
A lower dielectric layer 22 for accumulation of wall charges is formed on the lower substrate 18 having the address electrode 12X formed thereon. Barrier ribs 24 are formed on the lower dielectric layer 22. A phosphor layer 20 is covered on the surface of the lower dielectric layer 22 and the barrier rib 24. The barrier ribs 24 serve to prevent ultraviolet rays and a visible ray generated by a discharge from leaking toward a neighboring discharge cell. The phosphor layer 20 is excited by ultraviolet rays generated upon the discharge of gas to generate any one of red, green and blue visible rays. An insert gas is injected into a discharge space provided between the upper/lower substrates 10 and 18 and the barrier rib 24.
The pair of the sustain electrodes 12Y and 12Z formed on the underside of the upper substrate 10 consists of a transparent electrode 12a and a bus electrode 12b and intersect an address electrode 12X.
The transparent electrode 12a is formed of a transparent conductive material in order to shield light supplied from the discharge cell. The bus electrode 12b compensates for the conductivity of the transparent electrode 12a having a low conductivity due to relatively high resistance property.
An upper dielectric layer 14 and a protection film 16 are formed on the upper substrate 10 in which the pair of the sustain electrodes 12Y and 12Z are formed. The upper dielectric layer 14 has a wall charge accumulated thereon upon discharge. The protection film 16 serves to prevent damage of the upper dielectric layer 14 due to sputtering generated upon plasma discharge and also to increase discharge efficiency of secondary electrons. The protection film 16 is usually formed of magnesium oxide (MgO).
Such a discharge cell having the above structure is selected by an opposite discharge between the address electrode 12X and the scan/sustain electrode 12Y, and maintains a discharge by means of the surface discharge between the pair of the sustain electrodes 12Y and 12Z.
In this discharge cell, the phosphor layer 20 is light-emitted by means of ultraviolet rays generated upon sustain discharge, so that a visible ray is emitted to the outside of the cell. As a result, the discharge cell controls the period where the discharge is maintained to implement gray scale (also called “gradation”) and the PDP whose discharge cells are arranged in the form of a matrix displays an image.
FIGS. 4 to 7 illustrate a method for manufacturing a lower substrate of a conventional plasma display panel.
An address electrode 12X is formed on a lower substrate 18 by means of a photo method, a printing method, etc., as shown in FIG. 4. A paste in which a mixed powder having an oxide of a fine powder state mixed with PbO or non-PbO glass fine powder based on a composition ratio is mixed with an organic solvent is covered on the lower substrate 18 in which the address electrode 12X is formed by means of a screen-printing method. Thereafter, the paste covered on the lower substrate 18 is sintered at a given temperature to form a lower dielectric layer 22 on the lower substrate 18 having the address electrode 12X formed thereon, as shown in FIG. 5.
Barrier ribs 24 are formed on the lower dielectric layer 22 by means of a screen printing method, a sand blasting method, a pressing method, etc., as shown in FIG. 6.
Thereafter, a phosphor layer 20 is formed on the substrate on which the barrier ribs 24 and the lower dielectric layer 22 are formed by means of a screen printing method, a printing method and the like, as shown in FIG. 7.
The lower substrate of the PDP formed thus is closely adhered to the upper substrate by means of a sealing process (not shown).
In order to facilitate formation of a wall charge upon reset discharge, the upper dielectric layer of the conventional PDP contains a material of a high dielectric constant such as Pb (lead), Zr (zirconium), TiO3, etc. and the barrier rib also contains a material of a high dielectric constant such as Pb(lead), Zr(zirconium m), TiO3 and so on. Thereby, a number of wall charges are formed on the lateral sides of the barrier ribs 24 as well as the upper dielectric layer 14 upon reset discharge. However, since unwanted wall charges are formed on the barrier ribs of the PDP and the wall charges formed in a scan/sustain electrode 12Y are removed by these wall charges, erroneous discharge frequently occurs.
More specifically, during a reset period, a discharge occurs between the scan/sustain electrode 12Y and a common sustain electrode 12Z and between the scan/sustain electrode 12Y and the address electrode 12X. Therefore, during the reset period, a wall charge of the negative polarity is formed in the scan/sustain electrode 12Y, a wall charge of the positive polarity is formed in the common sustain electrode 12Z, and a wall charge of the positive polarity is formed in the address electrode 12X, respectively.
In the above, the barrier ribs 24 are formed of a material having a high dielectric constant. Thus, a wall charge is formed even in the barrier ribs 24 during the reset period, as shown in FIG. 8. In this case, wall charges 45 formed on the barrier ribs 24 are formed in the opposite polarity to a neighboring electrode. Accordingly, it serves to offset wall charges 55 of the electrode. That is, the amount of the wall charges 55 formed on the electrodes is reduced by means of the wall charges 45 formed on the barrier ribs 24.
Accordingly, since wall charges are sufficiently not formed on the electrodes during the reset period, an instable address discharge occurs. For this reason, an optical waveform A is shaken due to the address discharge, as shown in FIG. 9. Thereby, there occurs a problem in that the quality of an image is degraded since an erroneous discharge occurs in the PDP, which affects the image quality of a panel.